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Transactional Memory
Blekinge Tekniska Högskola, Sektionen för datavetenskap och kommunikation.ORCID-id: 0000-0001-9947-1088
Ansvarlig organisasjon
2010 (engelsk)Inngår i: Journal of Parallel and Distributed Computing, ISSN 0743-7315, E-ISSN 1096-0848, Vol. 70, nr 10, s. 993-1008Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exit for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.

sted, utgiver, år, opplag, sider
Elsevier , 2010. Vol. 70, nr 10, s. 993-1008
HSV kategori
Identifikatorer
URN: urn:nbn:se:bth-7687DOI: 10.1016/j.jpdc.2010.06.006ISI: 000281525100001Lokal ID: oai:bth.se:forskinfo01382CA13C76A091C1257801006294ABOAI: oai:DiVA.org:bth-7687DiVA, id: diva2:835331
Tilgjengelig fra: 2012-09-18 Laget: 2010-12-22 Sist oppdatert: 2018-02-02bibliografisk kontrollert

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