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Implementation and Evaluation of Update-Based Cache Protocols Under Relaxed Memory Consistency Models
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1995 (engelsk)Inngår i: Future Generations Computer Systems, ISSN 0167-739X , Vol. 11, nr 3, s. 247-271Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

The protocols of invalidation-based cache coherence have been extensively studied in the context of large-scale shared-memory multiprocessors. Under a relaxed memory consistency model, most of the write latency can be hidden whereas cache misses still incur a severe performance problem. By contrast, update-based protocols have a potential to reduce both write and read penalties under relaxed memory consistency models because coherence misses can be completely eliminated. This paper compares update- and invalidation-based protocols for their ability to reduce or hide memory access latencies and for their ease of implementation under relaxed memory consistency models.

sted, utgiver, år, opplag, sider
Amsterdam: North-Holland , 1995. Vol. 11, nr 3, s. 247-271
Emneord [en]
Multiprocessing systems, Buffer storage, Storage allocation (computer), Network protocols, Computer simulation, Synchronization, Computer hardware, Large scale systems, Performance
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Identifikatorer
URN: urn:nbn:se:bth-10087Lokal ID: oai:bth.se:forskinfo44852BCE2ED55610C12568A3002CAB4FOAI: oai:DiVA.org:bth-10087DiVA, id: diva2:838116
Tilgjengelig fra: 2012-09-18 Laget: 2000-03-15 Sist oppdatert: 2018-02-02bibliografisk kontrollert

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