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An Adaptive Update-Based Cache Coherence Protocol for Reduction of Miss Rate and Traffic
Responsible organisation
1994 (English)Conference paper, (Refereed) Published
Abstract [en]

Although directory-based write-invalidate cache coherence protocols have a potential to improve the performance of large-scale multiprocessors, coherence misses limit the processor utilization. Therefore, so called competitive-update protocols-hybrid protocols between write-invalidate and write-update-have been considered as a means to reduce the coherence miss rate and have been shown to be a better coherence policy for a wide range of applications. Unfortunately such protocols may cause high traffic peaks for applications with extensive use of migratory objects. These traffic peaks can offset the performance gain of a reduced miss rate if the network bandwidth is not sufficient. The authors propose to extend a competitive-update protocol with a previously published adaptive mechanism that can dynamically detect migratory objects and reduce the coherence traffic they cause. Detailed architectural simulations based on five scientific and engineering applications show that this adaptive protocol can outperform a write-invalidate protocol by reducing the miss rate and bandwidth need by as much as 71% and 26%, respectively.

Place, publisher, year, edition, pages
Athens, Greece: Springer , 1994.
Keyword [en]
cache storage, concurrency control, multiprocessing systems, parallel architectures, parallel processing, processor scheduling, protocols
National Category
Computer Science
Identifiers
URN: urn:nbn:se:bth-9650Local ID: oai:bth.se:forskinfoB33DC5E6DC6F9FB7C12568A3002CAB58ISBN: 3-540-58184-7 (print)OAI: oai:DiVA.org:bth-9650DiVA: diva2:837553
Conference
PARLE '94 : parallel architectures and languages Europe : proceedings July 4-8
Note
Also in Lecture Notes in Computer Science No. 817, pages 363-374, 1994Available from: 2012-09-18 Created: 2000-03-15 Last updated: 2015-06-30Bibliographically approved

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