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Modelling a 10 Gbits/Port Shared Memory ATM Switch
Responsible organisation
1997 (English)Conference paper, (Refereed) Published
Abstract [en]

The speed of optical transmission links is growing at a rate which is difficult for the microelectronic technology of ATM switches to follow. In order to cover the transmission rate gap between optical transmission links and ATM switches, ATM switches operating at multi Gbit/s rate have to be developed. A 10 Gbit/s/port shared memory ATM switch is under development at Linkoping Institute of Technology (LiTH) and Lund Institute of Technology (LTH) in Sweden. It has 8 inputs and 8 outputs. The switch will be implemented on a single chip in 0.8 μm BiCMOS. We report on a performance analysis of the switch under a specific traffic model. This traffic model emulates the LAN type of traffic. Performance analysis is crucial for evaluating and dimensioning the very high speed ATM switch

Place, publisher, year, edition, pages
Atlanta, Georgia, U.S.A. : IEEE , 1997.
National Category
Telecommunications
Identifiers
URN: urn:nbn:se:bth-9810Local ID: oai:bth.se:forskinfo8B041633B4DBEBC0C12568A3002CA9D6ISBN: 0-7803-4278-X (print)OAI: oai:DiVA.org:bth-9810DiVA: diva2:837758
Conference
Winter Simulation Conference
Note
This article is written under the Project "Modelling of Bursty Traffics"Available from: 2012-09-18 Created: 2000-03-15 Last updated: 2015-06-30Bibliographically approved

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Telecommunications

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf