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Development and evaluation of a framework for semi-automated formalization of automotive requirements.
Blekinge Institute of Technology, Faculty of Engineering, Department of Applied Signal Processing.
2015 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Quantity and intricacy of features implemented in vehicle have expanded rapidly over a past few years. Currently vision of autonomous vehicle is no longer a dream or SF movie, but instead a coming reality. In order to reach the better quality and high safety, advanced verification techniques are required. Simulink Design Verifier is a model checking tool based on formal verification, which can be effectively used to solve problems concerning error detection and testing at earlier stages of project. The transformation of requirements written in traditional form into Simulink Design Verifier objectives can be time consuming as well as requiring knowledge of system model and the verification tools.

In order to reduce time consumption and to guide a user through the system model and the verification tool, the semi-automated framework has been developed. An implementation of restricted English grammar patterns into Simulink objects supports description of patterns to engineers and reduces time consumption. The developed framework is flexible and intuitive hence can be a solution for other branches of industry, but further tests and verification would be required.

This thesis highlights the whole process of transformation system requirements written in natural language into Simulink Design Verifier objectives. The Fuel Level Display System model currently used by almost all Scania’s vehicles is analysed. Limitations and errors encountered during development process like a flexibility of Simulink Design Verifier to capture requirements and the patterns behaviour or ambiguity of system requirements are analysed and described in this thesis.

Place, publisher, year, edition, pages
2015.
Keyword [en]
matlab, simulink, requirements, simulink design verifier
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:bth-11644OAI: oai:DiVA.org:bth-11644DiVA: diva2:903805
Subject / course
ET2566 Master's Thesis (120 credits) in Electrical Engineering with emphasis on Signal processing
Educational program
ETASX Master of Science Programme in Electrical Engineering with emphasis on Signal Processing
Presentation
2015-06-26, E41, Gabriela Narutowicza 11/12, Gdansk, 09:00 (English)
Supervisors
Examiners
Available from: 2016-04-12 Created: 2016-02-16 Last updated: 2016-04-12Bibliographically approved

Open Access in DiVA

fulltext(4133 kB)57 downloads
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Type fulltextMimetype application/pdf

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Syrko, Ariel
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CiteExportLink to record
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
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