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Åleskog, ChristofferORCID iD iconorcid.org/0000-0002-0476-4177
Alternative names
Publications (3 of 3) Show all publications
Åleskog, C., Grahn, H. & Borg, A. (2024). A Comparative Study on Simulation Frameworks for AI Accelerator Evaluation. In: IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2024: . Paper presented at 2024 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2024, San Francisco, May 27-31 2024 (pp. 321-328). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>A Comparative Study on Simulation Frameworks for AI Accelerator Evaluation
2024 (English)In: IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2024, Institute of Electrical and Electronics Engineers (IEEE), 2024, p. 321-328Conference paper, Published paper (Refereed)
Abstract [en]

Domain-Specific Hardware Accelerators (DSHA) are natural components in the evolution of general computers. However, designing and simulating hardware in Hardware Description Languages (HDL) often requires more effort for the developers and might not be suitable in all scenarios, which makes high-level language-based software simulators for computer hardware attractive. Yet, choosing which simulation framework to use can be challenging due to the lack of comparative studies of high-level language-based simulators. This paper presents a comparative evaluation of state-of-the-art simulation frameworks that simulate computer hardware in high-level languages like C++. The contemporary simulators used in this study were selected from the 79 articles introducing novel AI accelerators referenced in our previous survey. We have identified six simulators that are suitable for AI accelerator evaluation, and provide a deeper analysis of three of them. © 2024 IEEE.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2024
Keywords
AI Accelerator, Comparative Study, Hardware Simulator, Simulation, C++ (programming language), Computer hardware, Computer simulation languages, Computer software, Comparatives studies, Domain specific, Hardware accelerators, Hardware simulators, High-level language, Higher-level languages, Simulation framework, Specific hardware, Computer hardware description languages
National Category
Computer Sciences
Identifiers
urn:nbn:se:bth-26819 (URN)10.1109/IPDPSW63119.2024.00073 (DOI)001284697300115 ()2-s2.0-85200768653 (Scopus ID)9798350364606 (ISBN)
Conference
2024 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2024, San Francisco, May 27-31 2024
Funder
ELLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications
Available from: 2024-08-16 Created: 2024-08-16 Last updated: 2025-09-30Bibliographically approved
Åleskog, C., Devagiri, V. M. & Boeva, V. (2022). A Graph-based Multi-view Clustering Approach for Continuous Pattern Mining. In: Witold Pedrycz and Shyi-Ming Chen (Ed.), Recent Advancements in Multi-View Data Analytics: (pp. 201-237). Springer Science+Business Media B.V.
Open this publication in new window or tab >>A Graph-based Multi-view Clustering Approach for Continuous Pattern Mining
2022 (English)In: Recent Advancements in Multi-View Data Analytics / [ed] Witold Pedrycz and Shyi-Ming Chen, Springer Science+Business Media B.V., 2022, p. 201-237Chapter in book (Refereed)
Abstract [en]

Today’s smart monitoring applications need machine learning models and data mining algorithms that are capable of analysing and mining the temporal component of data streams. These models and algorithms also ought to take into account the multi-source nature of the sensor data by being able to conduct multi-view analysis. In this study, we address these challenges by introducing a novel multi-view data stream clustering approach, entitled MST-MVS clustering, that can be applied in different smart monitoring applications for continuous pattern mining and data labelling. This proposed approach is based on the Minimum Spanning Tree (MST) clustering algorithm. This algorithm is applied for parallel building of local clustering models on different views in each chunk of data. The MST-MVS clustering transfers knowledge learnt in the current data chunk to the next chunk in the form of artificial nodes used by the MST clustering algorithm. These artificial nodes are identified by analyzing multi-view patterns extracted at each data chunk in the form of an integrated (global) clustering model. We further show how the extracted patterns can be used for post-labelling of the chunk’s data by introducing a dedicated labelling technique, entitled Pattern-labelling. We study and evaluate the MST-MVS clustering algorithm under different experimental scenarios on synthetic and real-world data. © 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.

Place, publisher, year, edition, pages
Springer Science+Business Media B.V., 2022
Series
Studies in Big Data, ISSN 2197-6503, E-ISSN 2197-6511 ; 106
Keywords
data stream, clustering analysis, pattern mining, minimum spanning tree
National Category
Computer Sciences
Identifiers
urn:nbn:se:bth-22261 (URN)10.1007/978-3-030-95239-6_8 (DOI)2-s2.0-85130970889 (Scopus ID)978-3-030-95239-6 (ISBN)
Available from: 2021-11-01 Created: 2021-11-01 Last updated: 2025-09-30Bibliographically approved
Åleskog, C., Grahn, H. & Borg, A. (2022). Recent Developments in Low-Power AI Accelerators: A Survey. Algorithms, 15(11), Article ID 419.
Open this publication in new window or tab >>Recent Developments in Low-Power AI Accelerators: A Survey
2022 (English)In: Algorithms, E-ISSN 1999-4893, Vol. 15, no 11, article id 419Article in journal (Refereed) Published
Abstract [en]

As machine learning and AI continue to rapidly develop, and with the ever-closer end of Moore’s law, new avenues and novel ideas in architecture design are being created and utilized. One avenue is accelerating AI as close to the user as possible, i.e., at the edge, to reduce latency and increase performance. Therefore, researchers have developed low-power AI accelerators, designed specifically to accelerate machine learning and AI at edge devices. In this paper, we present an overview of low-power AI accelerators between 2019–2022. Low-power AI accelerators are defined in this paper based on their acceleration target and power consumption. In this survey, 79 low-power AI accelerators are presented and discussed. The reviewed accelerators are discussed based on five criteria: (i) power, performance, and power efficiency, (ii) acceleration targets, (iii) arithmetic precision, (iv) neuromorphic accelerators, and (v) industry vs. academic accelerators. CNNs and DNNs are the most popular accelerator targets, while Transformers and SNNs are on the rise.

Place, publisher, year, edition, pages
MDPI, 2022
Keywords
survey; hardware accelerator; low-power; performance; machine learning; artificial intelligence; neural networks
National Category
Computer Sciences
Research subject
Computer Science
Identifiers
urn:nbn:se:bth-24171 (URN)10.3390/a15110419 (DOI)000930705100001 ()
Funder
ELLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications, C05Knowledge Foundation, 20170236
Note

open access

Available from: 2023-01-09 Created: 2023-01-09 Last updated: 2025-09-30Bibliographically approved
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ORCID iD: ORCID iD iconorcid.org/0000-0002-0476-4177

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